The present invention relates to a magnetic memory device arranged using magnetic thin-film memory elements, a method for writing on such a magnetic memory device and a method for reading from such a magnetic memory device.
Volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM) are hitherto used as general-purpose memories for use in information processing equipment such as computers and mobile communication tools. All information in such volatile memories is lost unless a current is always supplied to the volatile memories. It is therefore necessary to provide means for storing information, that is, nonvolatile memories, such as flash EEPROM and hard disk units. Increase in the access speed of such nonvolatile memories with higher speed information processing becomes an important issue. Further, with rapider diffusion and higher performance of portable information equipment, information equipment aimed at so-called ubiquitous computing, that is, aimed at being capable of carrying out information processing anytime and anywhere, has been developed rapidly. Development of high-speed nonvolatile memories is demanded earnestly as a key device in developing such equipment.
MRAM (Magnetic Random Access Memory) is known as technology effective in increasing the speed of nonvolatile memories. MRAM is comprised of memory cells arrayed in a matrix and each constituted by a magnetic element including two ferromagnetic layers. In each memory cell, information is stored by bringing the magnetization directions of the ferromagnetic layers of the element into a parallel state (in same direction) or anti-parallel state (in opposite direction) to their easy axes of magnetization correspondingly to binary information of “0” or “1”. The resistance value of the magnetic element in a specific direction when the magnetization directions of the ferromagnetic layers are parallel differs from that when they are antiparallel. Accordingly, information can be read from the memory cell by detecting a difference in resistance corresponding to information as a change in current or voltage. Due to operation on such a principle, it is essential in MRAM that the rate of change in resistance is as high as possible in order to perform stable writing/reading.
MRAM put into practical use currently uses GMR (Giant Magneto-Resistive). GMR is a phenomenon that the resistance value is minimized when the magnetization directions of two magnetic layers disposed to have parallel easy axes of magnetization are parallel along the easy axes of magnetization, and the resistance value is maximized when the magnetization directions of the two magnetic layers are antiparallel. For example, the technique disclosed in U.S. Pat. No. 5,343,422 is known as MRAM using GMR elements (hereinafter abbreviated to “GMR-MRAM”).
GMR-MRAM includes a Pseudo Spin Valve Type and a Spin Valve Type. In Pseudo Spin Valve Type MRAM, each GMR element is made of a laminate of two ferromagnetic layers and a nonmagnetic layer sandwiched therebetween, for writing/reading information using a difference in coercive force between the two ferromagnetic layers. On the other hand, in Spin Valve Type MRAM, two ferromagnetic layers are comprised of a fixed layer having a fixed magnetization direction and a free layer having a magnetization direction variable in accordance with an external magnetic field. The fixed layer is antiferromagnetically coupled with an antiferromagnetic layer in the condition that a nonmagnetic layer sandwiched between the fixed layer and the antiferromagnetic layer, so that the magnetization of the fixed layer is fixed stably. In terms of the rates of change in resistance of the GMR elements of those types, a Pseudo Spin Valve Type element having a laminate structure of (NiFe/Cu/Co) is about 6-8%, and even a SpinValve Type element having a laminate structure of (PtMn/CoFe/Cu/CoFe) is about 10%. For this reason, a sufficient reading output using a difference in resistance as a difference in current or voltage cannot be obtained, and it is regarded as difficult to improve the storage capacity or the access speed.
With regard to this point, MRAM using TMR (Tunneling magneto-resistive) (hereinafter abbreviated to “TMR-MRAM”) can increase the rate of change in resistance on a large scale. TMR is a phenomenon that a tunnel current flowing in an ultrathin insulating layer in a laminate in which the ultrathin insulating layer is sandwiched between two ferromagnetic layers (a fixed layer having a fixed magnetization direction and a magnetosensitive layer having a variable magnetization direction, that is, a free layer) changes in accordance with the relative angle of the magnetization directions with each other. That is, the tunnel current is maximized (with a minimal resistance value of the cell) when the magnetization directions are parallel to each other, while the tunnel current is minimized (with a maximal resistance value of the cell) when the magnetization directions are antiparallel. For specific example, the rate of change in resistance in a laminate structure of CoFe/Al-oxide/CoFe known as TMR element reaches 40% or more.
In addition, when the TMR element is combined with a semiconductor device such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is regarded as easy to match them with each other because the TMR element has high resistance. From such advantages, TMR-MRAM is easier to increase its output and can be expected to have higher storage capacity and higher access speed than GMR-MRAM. As for TMR-MRAM, techniques disclosed in U.S. Pat. No. 5,629,922 and Japanese Patent Publication 9-91949/(1997).
For writing information, TMR-MRAM adopts such a system that the magnetization direction of the ferromagnetic layer is changed using a current magnetic field induced by a current flowing through a conductor. Thus, binary information is stored in accordance with the relative magnetization direction (parallelism or antiparallelism) between the ferromagnetic layers. For reading the stored information, TMR-MRAM adopts such a system that a current is applied to the insulating layer in a direction perpendicular to the layer surface, and a tunnel current value or a tunnel resistance value is detected. In this case, the difference in relative magnetization direction (parallelism or antiparallelism) between the ferromagnetic layers appears as a difference in an output current value or a cell resistance value.
As for the cell array structure, there has been proposed a structure in which a plurality of TMR elements are connected in parallel on a data line, and a selection semiconductor device is then disposed correspondingly to each TMR element, or a structure in which such a semiconductor device is disposed for each of such data lines. Available as the semiconductor device is a diode formed out of MOSFET or FET short-circuited between its gate and drain, a PN-junction diode, a Schottky diode, or the like. In addition, there has been proposed a structure in which TMR elements are disposed in a matrix using row data lines and column data lines, and a selection transistor is disposed for each data line.
Of those structures, the structure in which a selection semiconductor device is disposed for each TMR element has the most excellent properties from the point of view of the efficiency of power consumption in reading. However, when there is a variation in properties among the semiconductor devices, noise generated due to the variation is not negligible. In addition, also in consideration of noise linked with the data lines, noise generated due to the variation of properties among sense amplifiers and noise generated in peripheral circuits due to feedback from a power supply circuit, there is a possibility that the S/N ratio of the output voltage from the memory cell reaches only about several dB.
Therefore, in order to improve the S/N ratio of the reading output, the cell array of TMR-MRAM has been improved as follows.
A method based on differential amplification of a differential voltage Vsig obtained by comparing an output voltage V of a selected memory cell with a reference voltage Vref is often used. The differential amplification is intended firstly to eliminate noise generated in a pair of data lines the memory cell is connected, and secondly to eliminate an offset of the output voltage caused by the variation of properties among semiconductor devices for driving sense lines or for selecting a cell. However, a circuit for generating the reference voltage Vref is implemented by a circuit using a dummy cell or a semiconductor device, and since there is a variation of device properties between this circuit and the memory cell, it is impossible in theory to eliminate the offset of the output voltage perfectly.
To solve this problem, a method in which each memory cell is formed out of a pair of TMR elements and the differential output from the paired elements is amplified is generally known broadly. In this method, writing is done so that the magnetization direction of a magnetosensitive layer of each of the paired TMR elements is always antiparallel to that of the other. That is, complementary writing is performed so that the magnetization direction of the magnetosensitive layer is parallel to the magnetization direction of the fixed layer in one of the elements, while the magnetization directions of the two layers are antiparallel to each other in the other element. A differential output of the two elements is then amplified and read. Thus, the common mode noise is eliminated so that the S/N ratio is improved. The configuration of such a differential amplification type circuit is disclosed in Japanese Patent Publication 2001-236781, Japanese Patent Publication 2001-266567, or International Solid-State Circuits Conference(ISSCC) 2000 Digest paper TA7.2.
By way of more specific example, in the technique disclosed in the Patent Documents JP-2001-236781 and JP-2001-266567, first and second TMR elements constituting a memory cell are connected at one ends to a pair of first and second data lines respectively, while connected at the other ends to a bit line through one and the same cell selection semiconductor device. A word line is connected to the cell selection semiconductor device. For reading information, a difference in potential is provided between the bit line and each of the first and second data lines while the potential of the first data line is kept equal to the potential of the second data line. Thus, a differential value in current flow rate between the first and second data lines is set as an output.
Generally in such a differential amplification system, however, the variation in resistance value between the paired TMR elements becomes a problem. The variation in resistance between the TMR elements occurs in a manufacturing process, and a current error caused by the variation in resistance is inevitable. As a result, the S/N ratio of an output signal deteriorates compulsively.
In the wiring structure, a large number of TMR elements are connected to the first and second data lines, and cell selection semiconductor devices are connected to the third bit line correspondingly to the number of cells arrayed in the bit array direction, so that a matrix of memory cells are formed. Thus, in order to obtain a stable read signal output, it is necessary to suppress the variation in resistance among the TMR elements connected to each data line and the variation in properties among the selection semiconductor devices connected to the same bit line sufficiently. However, the reading method in which a voltage difference of equal potential is given to the first and second data lines is not designed to be able to suppress those variations on principle. Therefore, there has been a problem that it is very difficult to take thoroughgoing countermeasures against noise generated due to such variations.
For such a reason, the S/N ratio of read signals cannot be improved sufficiently in related-art MRAM in spite of measures proposed one after another. As a result, in fact, a sufficient output voltage cannot be obtained though TMR elements have a rate of change in resistance reaching about 40%. That is, when the present memory structure is used as it is, not only does it have a problem on the operating stability such as reading accuracy, but it is also estimated to be incapable to support higher density of memories satisfactorily.
Incidentally, as described above, various measures about the method for reading from TMR-MRAM or the configuration of a reading circuit have been taken, but the structure of TMR elements themselves has not been improved remarkably so far.